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Integrated Circuit Systems, Inc.
ICS9150-04
Pentium ProTM and SDRAM Frequency Generator
General Description
The ICS9150-04 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are selectable from 50 to 83.3MHz. Features include five CPU, seven PCI and Sixteen SDRAM clocks. One reference output is available equal to the crystal frequency, plus three IOAPIC outputs powered by VDDL1. One 48 MHz for USB is provided plus a 24 MHz. Spread Spectrum built in up to 1.5% modulation to reduce EMI. Serial programming I2C interface allows changing functions, stop clock programing and Frequency selection. Rise time adjustment for VDD at 3.3V or 2.5V CPU. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 505% duty cycle. The REF 24 and 48 MHz and SDRAM 12, 13 clock outputs typically provide better than 0.5V/ns slew rates.
Features
Generates five processor, six bus, one 14.31818MHz (3.3V) three IOAPIC, 16 SDRAM clocks, 48MHz USB clock and 24MHz Super I/O clock. Synchronous clocks skew matched to 250 ps window on CPUCLKs and 500ps window on PCICLKs Skew from CPU (earlier) to PCI clock - 1 to 4ns, 2.6ns nom. Power Management Control Input pins when MODE Low VDD(1:4) - 3.3V 10% (inputs 5V tolerant w/series R ) VDDL(1:2) - 2.5V or 3.3V 5% I2C interface for programming stopclocks plus spread spectrum options (0.5% or 1.5%, center spread or down spread) 56-pin SSOP package
Pin Configuration
Block Diagram
56-Pin SSOP
Power Groups
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation.
VDD1 = REF, X1, X2 VDD2 = PCICLK_F, PCICLK(0:5) VDD3 = SDRAM (0:15), supply for PLL core, VDD4 = 48MHz, 24MHz VDDL1 = IOAPIC (0:2) VDDL2 = CPUCLK (0:4)
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
9150-04 RevD 07/27/98
ICS9150-04
Pin Descriptions
PIN NUMBER PIN NAME IOAPIC2 CPU3.3#_2.5 TYPE DESCRIPTION OUT IOAPIC clock output (14.318MHz) powered by VDDL1 Indicates whether VDDL1 & VDDL2 are 3.3 or 2.5V. Output buffer strength compensates for VDDL selection to maintain IN CPU to SDRAM skew. High = 2.5V, Low = 3.3V. Has pull-up to VDDL1, must use series resistor for 3.3 or 5V logic levels. OUT 14.318 MHz reference clock outputs. PWR IN OUT OUT IN OUT IN OUT IN IN OUT IN OUT IN PWR PWR OUT OUT OUT OUT IN OUT IN Ground. 14.318MHz input. Has internal load cap, (nominal 33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 Free running BUS clock during PCI_STOP#=0. Latched frequency select input. Has pull-up to VDD2. BUS clock output Latched frequency select input. Has pull-up to VDD2. BUS clock outputs. Serial data in for serial config port. (I2C) Clock input for serial config port. (I2C) 24MHz clock output for Super I/O or FD. Latched frequency select input. Has pull-up to VDD4. 48MHz clock output for USB. Latched input for MODE select. Converts 2 outputs to power management CPU_STOP# and PCI_STOP# when low. Has pullup to VDD4. Nominal 3.3V power supply, see power groups for function. CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V nominal. SDRAM clocks IOAPIC clock output. (14.318 MHz) Poweredby VDDL1 CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz) IOAPIC clock output. (14.31818 MHz) Powered by VDDL1 Halts CPUCLK clocks at logic "0" level when low. (in mobile, MODE=0) PCI BUS clock 5 Halts PCICLK (0:4) at logic "0" level when low. (in mobile, MODE=0)
2
3 REF0 4, 10, 17, 23, 31, 34, GND 40, 47, 53 5 6 8 9 11, 12, 13, 14 27 28 30 X1 X2 PCICLK_F FS11 PCICLK0 FS21 PCICLK (1:4) SDATA SCLK 24MHz FS01 48MHz 29 MODE1
1, 7, 15, 20, 26, 37, VDD2, VDD1, 43 VDD3, VDD4 50, 56 VDDL2, VDDL1
18, 19, 21, 22, 24, 25, 32, 33, 35, 36, SDRAM (0:15) 38, 39, 41, 42, 44, 45 55 IOAPIC0 46, 48, 49, 51, 52 CPUCLK (0:4) IOAPIC1 54 CPU_STOP# PCICLK5 16 PCI_STOP#
Notes: 1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9150-04
Definitions 5 Latched Inputs at Internal Power-On Reset:
Pin shared as MODE ................................ 48MHz/MODE CPU 3.3_2.5#V .................. IOAPIC2/CPU3.3#_2.5 FS0 ..................................... 24MHz/FS0 FS1 ..................................... PCICLK_F/FS1 FS2 ..................................... PCICLK0/FS2
2 Realtime Inputs
Pins 27, 28 - I2C Serial input SDATA & SCLK
Pull-ups
2 pins with input latch or I/O have IOAPIC output function with VDDL1 which can be at 2.5V or 3.3V. These inputs will have to use series resistor (above 100) to external VIN to be 3.3 & 5V logic input tolerant. PMOS output stage provides input clamp diode to VDDL.
Nwell resistor Pull-ups 100 to 150K to local VDD (ie on IOAPIC pins use VDDL1, on FS1, 2 use VDD2, FS0=VDD4 and PCI_STOP#)
Functionality
VDD1,2,3 = 3.3V5%, VDDL1,2 = 2.5V5% or 3.35%, TA=0 to 70C Crystal (X1, X2) = 14.31818MHz
FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU, SDRAM(MHz) 66.8 60.0 75.0 83.3 68.5 83.3 75.0 50.0 PCICLK (MHz) 33.4 (1/2 CPU) 30.0 (1/2 CPU) 37.5 (1/2 CPU) 33.3 34.25 (1/2 CPU) 41.65 (1/2 CPU) 32 25.0 (1/2 CPU) REF, IOAPIC (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
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ICS9150-04
Mode Pin - Power Management Input Control
MODE, Pin 55 0 1 Pin 54 CPU_STOP# Input IOAPIC1 Output Pin 16 PCI_STOP# Input PCICLK5 Output
Power Management Functionality
CPU_STOP# PCI_STOP# CPUCLK Outputs Stopped Low Stopped Low Running Running PCICLK_F, PCICLK(0:5) REF, IOAPIC Outputs 48MHz and SDRAM Stopped Low Running Stopped Low Running Running Running Running Running Crystal OSC Running Running Running Running VCO
0 0 1 1
0 1 0 1
Running Running Running Running
Spread Spectrum Functionality
BYTE0, Bit1 BYTE0, Bit2 BYTE0, Bit7 SS_EN SS_TYPE 0 0 1 1 0 1 1 0 X X CPU, SDRAM and PCI CLOCKS Frequency modulated in center spread spectrum mode +1.5%, -1.5% Frequency modulated in center spread spectrum mode +0.5%, -0.5% Frequency modulated in down spread spectrum mode +0%, -3.0% Frequency modulated in down spread spectrum mode +0%, -1.0% Normal, Steady frequency mode REF, IOAPIC 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 24,48MHz 24,48MHz 24,48MHz 24,48MHz 24,48MHz 24,48MHz
CPU 3.3#_2.5V Buffer selector for CPUCLK driver.
CPU3.3#_2.5 Latched Input Level 1 0 Buffer Selected for Operation at: 2.5V VDD 3.3V VDD
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ICS9150-04
Technical Pin Function Descriptions
VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF, PCICLK, and SDRAM. This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL1,2 This is the power supply for the CPUCLK and IOAPIC output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. With nominal value of 33pF no external load cap is needed for a CL=17 to 18pF crystal. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is nominally 33pF. CPUCLK (0:4) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks is controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. SDRAM(0:15) These Output Clocks are used to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the SDRAMs output is controlled by the supply voltage that is applied to VDD3 of the device. Operates at 3.3 volts. IOAPIC (0:2) These Outputs are fixed frequency Output Clocks that run at the Reference Input frequency (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. REF0 The REF Output is a fixed frequency Clock that runs at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equal to PCICLK(0:5). It is FREE RUNNING, and will not be stopped by PCI_STOP#. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency, for most choices of FS (0:2). FS(0:2) These Input pins control the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. These inputs are Bidirectional Input/Output pins, latched at internal power-onreset. MODE This Input pin is used to select the Input function of the I/O pins. An active Low will place the I/O pins in the Input mode and enable the stop clock functions. (This is the Power Management Mode) CPU_STOP# This is a synchronous active Low Input pin used to stop the CPUCLK clocks in an active low state. All other Clocks including SDRAM clocks will continue to run while this function is enabled. The CPUCLKs will have a turn ON latency of at least 3 CPU clocks. This input pin valid only when MODE=0 (Power Management Mode) PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK clocks in an active low state. It will not effect PCICLK_F nor any other outputs. This input pin valid only when MODE=0 (Power Management Mode) I2C (SDATA, SCLK) The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I 2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C specification in Philips I2C Peripherals Data Handbook (1996) should be followed. 48MHz This is a fixed frequency Clock output at 48MHz that is typically used to drive USB devices. 24MHz This pin is a fixed frequency clock output typically used to drive Super I/O devices. CPU 3.3#_2.5 This Input pin controls the CPU output buffer strength for skew matching CPU and SDRAM outputs to compensate for the external VDDL supply condition. It is important to use this function when selecting power supply requirements for VDDL1,2. A logic 1 (ground) will indicate 2.5V operation and a logic 0 will indicate 3.3V operation. This pin has an internal pullup resistor to VDD.
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ICS9150-04
General I2C serial interface information 2
A.
Clock Generator Address (7 bits)
For the clock generator to be addressed by an I C controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte. Then Byte 0, 1, 2, etc in sequence until STOP.
A(6:0) & R/W# D2(H)
B.
ACK
+ 8 bits dummy command code
ACK
+ 8 bits dummy Byte count
ACK
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB PIIX4 protocol.
Clock Generator Address (7 bits)
A(6:0) & R/W# D3(H)
C. D. E. F.
ACK
Byte 0
ACK
Byte 1
ACK
Byte 0, 1, 2, etc in sequence until STOP.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. The Fixed clocks 24, 48MHz are not addressable in the registers for Stopping. These outputs are always running, except in Tristate Mode. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default to a 1 (Enabled output state)
G . H.
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default bits 0-3 to logic 0)
Bit Bit 7 Description 0 - 1.5% Spread Spectrum Modulation 1 - 0.5% Spread Spectrum Modulation Bit6 Bit5 Bit4 CPU clock PCI 111 66.8 33.4(1/2 CPU) 60.0 30.0 (1/2 CPU) 110 101 75.0 37.5 (1/2 CPU) 100 83.3 33.3 011 68.5 34.5 (1/2 CPU) 010 83.3 41.65 (1/2 CPU) 001 75.0 32.0 000 50.0 25.0 (1/2 CPU) 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 6:4 (above) 0 - Spread Spectrum center spread type. (default) 1 - Spread Spectrum down spread type. Bit1 Bit0 1 1 - Tri-State 1 0 - Spread Spectrum Enable 0 1 - Testmode 0 0 - Normal Operation PWD 0
Note 1. Default at Power-up will be for latched logic inputs to define the frequency. Bits 4, 5, 6 are default to 000. If bit 3 is written to a 1 to use Bits 6:4, then these should be defined to the desired frequency at same write cycle.
Bit 6:4
Note 1
Note: PWD = Power-Up Default
0 0 0 0
Bit 3 Bit 2 Bit 1 Bit 0
I2C is a trademark of Philips Corporation
6
ICS9150-04
Select Functions
FUNCTION DESCRIPTION
OUTPUTS CPU PCI, PCI_F Hi-Z TCLK/41 SDRAM REF IOAPIC
Tri - State Test Mode
Hi-Z TCLK/21
Hi-Z TCLK/21
Hi-Z TCLK1
Hi-Z TCLK1
Notes: 1. REF is a test clock on the X1 inputs during test mode.
Byte 1: CPU Clock Register
Byte 2: PCICLK Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD DESCRIPTION 1 Reserved 1 Reserved 1 Reserved 46 1 CPUCLK4 (Act/Inact) 48 1 CPUCLK3 (Act/Inact) 49 1 CPUCLK2 (Act/Inact) 51 1 CPUCLK1 (Act/Inact) 52 1 CPUCLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 8 1 PCICLK_F (Act/Inact) PCICLK5 (Act/Inact) Bit 5 16 1 Desktop Mode Only Bit 4 14 1 PCICLK4 (Act/Inact) Bit 3 13 1 PCICLK3 (Act/Inact) Bit 2 12 1 PCICLK2 (Act/Inact) Bit 1 11 1 PCICLK1 (Act/Inact) Bit 0 9 1 PCICLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 3: SDRAM Clock Register
Byte 4: SDRAM Clock Register
BIT PIN# PWD DESCRIPTION Bit 7 35 1 SDRAM7 (Act/Inact) Bit 6 36 1 SDRAM6 (Act/Inact) Bit 5 38 1 SDRAM5 (Act/Inact) Bit 4 39 1 SDRAM4 (Act/Inact) Bit 3 41 1 SDRAM3 (Act/Inact) Bit 2 42 1 SDRAM2 (Act/Inact) Bit 1 44 1 SDRAM1 (Act/Inact) Bit 0 45 1 SDRAM0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD DESCRIPTION 24 1 SDRAM15 (Act/Inact) 25 1 SDRAM14 (Act/Inact) 32 1 SDRAM13 (Act/Inact) 33 1 SDRAM12 (Act/Inact) 18 1 SDRAM11 (Act/Inact) 19 1 SDRAM10 (Act/Inact) 21 1 SDRAM9 (Act/Inact) 22 1 SDRAM8 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
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ICS9150-04
Byte 5: Peripheral Clock Register Byte 6: Peripheral Clock Register
BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 2 1 IOAPIC2 (Act/Inact) IOAPIC1 (Act/Inact) Bit 5 54 1 Desktop Mode Only Bit 4 55 1 IOAPIC0 (Act/Inact) Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 1 Reserved Bit 0 3 1 REF0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
BIT PIN# PWD DESCRIPTION Bit 7 1 Reserved Bit 6 1 Reserved Bit 5 1 Reserved Bit 4 1 Reserved Bit 3 1 Reserved Bit 2 1 Reserved Bit 1 1 Reserved Bit 0 1 Reserve
Notes: 1. Byte 6 is reserved by Integrated Circuit Systems for future applications.
ICS9150-04 Power Management Requirements
SIGNAL
SIGNAL STATE
CPU_ STOP# PCI_STOP#
0 (Disabled)2 1 (Enabled)1 0 (Disabled)2 1 (Enabled)1
Latency No. of rising edges of free running PCICLK 1 1 1 1
Notes. 1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
8
ICS9150-04
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS9150-04. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS9150-04. 3. All other clocks continue to run undisturbed. 4. PCI_STOP# is shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9150-04. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9150-04 internally. The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9150 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9150. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
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ICS9150-04
Shared Pin Operation Input/Output Pins
Pins 2, 8, 9, 29 and 30 on the ICS9150-04 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device's internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
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ICS9150-04
Fig. 2a
Fig. 2b
11
ICS9150-04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization Skew
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP Fi CIN CINX Ttrans Ts TSTAB
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq.
0.1 2.0 -100 135 14.318
MAX VDD+0.3 0.8 5
UNITS V V A A A mA MHz
160
27
36
5 45 2 2
pF pF ms ms ms ps ns
TCPU-SDRAM1 VT = 1.5 V; VDD = 3.3; 66.8 MHz; SDRAM Leads TCPU-PCI1 VT = 1.5 V;
200 1 2.2
350 4
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) SYMBOL CONDITIONS IDD2.5OP CL = 0 pF; Select @ 66M V = 1.5V; VTL = 1.25V; VDDL = 2.5; Operating Supply TCPU-SDRAM2 T 1 66.8MHz; SDRAM Leads Current Skew TCPU-PCI2 V T = 1.5V; VTL = 1.25V; CPU Leads
1
PARAMETER
MIN
TYP 5 500
MAX 30 800 4
UNITS mA ps ns
1
2.5
Guarenteed by design, not 100% tested in production.
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ICS9150-04
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Single Edge Displacement2 Jitter, One Sigma Jitter, Absolute
1
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B
1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 12 mA VOH = 2.0 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 10 10 2
TYP
MAX 25 25
UNITS V V mA mA ns ns % ps ps ps ps
19
2.2 0.3 -20 26 2.5 1.6
0.4 -16 3 2 55 250 300 150 300
dt2B1 tsk2B1 tjsed2B1 tj1s2B tjabs2B1
1
43
46 60 200 80
-300
80
Guaranteed by design, not 100% tested in production. 2 Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Single Edge Displacement 2 Jitter, One Sigma Jitter, Absolute SYMBOL R DSP2A1 R DSN2A1 VOH2A VOL2A IOH2A IOL2A t r2A1 t f2A1 d t2A1 t sk2A1 CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -28 mA IOL = 27 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V 45 MIN 10 10 2.5 2.6 0.35 -29 37 1.9 1.4 48 80 200 60 -300 200 TYP MAX 20 20 0.4 -23 2.5 2 55 250 250 150 300 UNITS V V mA mA ns ns % ps ps ps ps
33
tjsed2A1 VT = 1.25 V t j1s2A1 t jabs2A1 VT = 1.5 V VT = 1.5 V
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ICS9150-04
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma
1
SYMBOL RDSP1
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V, synchronous, excluding select 4 VT = 1.5 V, synchronous, select 4 VT = 1.5 V, asynchronous, select 1 VT = 1.5 V, synchronous, excluding select 4 VT = 1.5 V, synchronous, select 4 VT = 1.5 V, asynchronous, select 1
MIN 12 12 2.4
TYP
MAX 55 55
UNITS V V mA mA ns ns % ps ps ps ps ps ps ps
RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1 1 1
41
3 0.2 -60 50 1.4 1.3
0.4 -40 2 2 55 500 150 550 250 250 700 500
dt1
45
49 80 30 385 175
tsk1
tj1s1 tj1s1a tj1s1b tjabs1 tj1s1a tjabs1b
Jitter, Absolute
1
-250 -700 -500
100 510 390
1
Guarenteed by design, not 100% tested in production.
14
ICS9150-04
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance 10 RDSP3 1 VO = VDD*(0.5) 1 Output Impedance VO = VDD*(0.5) 10 RDSN3 Output High Voltage VOH3 IOH = -28 mA (except SDRAM12,13) 2.4 VOH3a IOH = -16 mA (SDRAM12,13) 2.4 Output Low Voltage VOL3 IOL = 23 mA (except SDRAM12,13) VOL3a IOL = 9 mA (SDRAM12,13) Output High Current IOH3 VOH = 2.0 V (except SDRAM12,13) IOH3a VOH = 2.0 V (SDRAM12,13) Output Low Current IOL3 VOL = 0.8 V (except SDRAM12,13) 41 IOL3a VOL = 0.8 V (SDRAM12,13) 16 Rise Time Tr3 1 Tr3a1 Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
TYP
MAX 24 24
3 2.6 0.2 0.3 -60 -32 50 25 1.2 2.5 1.1 2.7 51 285 50 -
0.4 0.4 -40 -22
UNITS V V V V mA mA mA mA ns ns ns ns % ps ps ps
VOL = 0.4 V, VOH = 2.4 (except SDRAM12,13) VOL = 0.4 V, VOH = 2.4 V (SDRAM12,13) VOH = 2.4 V, VOL = 0.4 (except SDRAM12,13) VOH = 2.4 V, VOL = 0.4 V (SDRAM12,13) VT = 1.5 V VT = 1.5 V (except SDRAM12,13) VT = 1.5 V VT = 1.5 V 45
2 4 2 4 57 500 150 250
Tf3 1 Tf3a1 Dt3 1 Tsk3 1 Tj1s3 1 Tjabs3 1
-250
Guaranteed by design, not 100% tested in production.
15
ICS9150-04
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL RDSP4B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 10 10 2
TYP
MAX 30 30
UNITS V V mA mA ns ns % ps % %
RDSN4B VOH4\B VOL4B IOH4B IOL4B
19
2.1 0.3 -20 26 1.9 1.5
0.4 -16 4 3.2 55 250 3 5
tr4B1 tf4B1 dt4B1 tsk4B1 tj1s4B1 tjabs4B1
45
53 60 1
-5
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 10 - 20 pF (unless otherwise stated) PARAMETER Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, One Sigma Jitter, Absolute
1
SYMBOL FO4 RDSP4A1 RDSN4A1 VOH4A VOL4A IOH4A IOL4A tr4A1 tf4A1 d t4A1 tsk4A1 tj1s4A1 tjabs4A1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.25 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4
TYP 14.318
MAX 30 30
UNITS MHz V V mA mA ns ns % ps % %
16
2.6 0.3 -32 25 1.8 2.2
0.4 -22 4 4 57 250 3 5
45
53 60 1
-5
-
Guaranteed by design, not 100% tested in production.
16
ICS9150-04
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; C L = 10 -20 pF (unless otherwise stated) PARAMETER Output Frequency Output Frequency Output Frequency Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL FO24M FO48M FOREF RDSP5 1 RDSN5 VOH5 VOL5 IOH5 IOL5 tr5
1 1
CONDITIONS
MIN
TYP 24 48 14.318
MAX
UNITS MHz MHz MHz V V mA mA ns ns % % %
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
20 20 2.4 2.6 0.3 -32 25 1.7 2.1 45 -5 54 1 -
60 60 0.4 -22 4 4 57 3 5
16
t f5 1 dt5
1 1
tj1s5 tjabs5 1
Guaranteed by design, not 100% tested in production.
17
ICS9150-04
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
18
ICS9150-04
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N
X
COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .010 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100
VARIATIONS AC AD MIN. .620 .720
D NOM. .625 .725
N MAX. .630 .730 48 56
Ordering Information
ICS9150F-04
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
19
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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